1. Field of the Invention
The present invention relates to a chip-stacked package structure, and more particularly, to form a chip-stacked package structure with lead-frame.
2. Description of the Prior Art
In semiconductor post-processing, many efforts have been made for increasing scale of the integrated circuits such as memories while minimizing the occupied area. Accordingly, the development of three-dimensional (3D) packaging technology is in progress and the idea of making up a chip-stacked structure has been disclosed.
The prior art has taught that a chip-stacked structure can be formed by firstly stacking a plurality of chips and then electrically connecting the chips to the substrate in wire bonding process. FIG. 1 shows a chip-stacked package structure that using lead-frame as a substrate, wherein FIG. 1A is a cross-sectional view and FIG. 1B is a plane view of FIG. 1A. As shown in FIG. 1A, lead-frame 5 is composed of inner lead portion 5a, outer lead portion 5b, and a platform portion 5c, wherein platform portion 5c is vertically distant from the inner lead portion 5a and outer lead portion 5b. Firstly, three chips are first stacked on inner lead 5a of lead-frame 5, and then metal wires 10, 11, and 12 are provided for connecting the pads 7, 8, and 9 on three chips to the platform portion 5c of lead-frame 5. The molding process is then performed for covering three stacked chips and inner lead 5a and part of platform portion 5c of lead-frame 5. The outer lead portion 5b is exposed to serve as leads connecting other interfaces.
In prior chip-stacked package structure as described above, the metal wires 10, 11, and 12 between each chip and the platform portion 5c of lead-frame 5 have different lengths and bending degrees. Therefore, in the molding process, not only metal wires of greater length and larger bending degree may shift and cause chips to become short but changes in the phase of electric signals would be also occurred.